Schedulability analysis for electronic designs has become increasingly important, especially when dealing with large complex multi-protocol network designs and verification. One specific type of schedulabilty analysis within the domain of Real-Time science determines a worst-case latency of packetized communication through a communication bus described in the electronic designs. Computing systems often employ dedicated and often very complex worst-case latency calculation algorithms, such as a Trajectory Approach algorithm, to determine a worst-case latency metric for an electronic design.
Practical usability of the Trajectory Approach, however, has been seriously limited when applied to sizable real-life systems, as the execution time of this type of worst-case latency calculation algorithm increases dramatically, often exponentially, with expanding state-space. This exponential increase of the execution time is often caused by the fact that the worst-case latency calculation algorithms take into consideration all blocking factors and then utilize the results recursively for calculations, e.g., such as end-to-end worst-case latency or the like.
There are less computation-intensive or “fast” algorithms, such as Network Calculus algorithm, which can provide a worst-case latency metric for sizable real-life systems. This resulting worst-case latency metric, however, is often overly pessimistic, causing designers to relax timing requirements of their electronic designs and inefficiently utilize available bandwidth. Thus, when tasked with identifying a worst-case latency metric in a sizable real-life system, designers have to trade-off speed and accuracy. As an example, the Trajectory Approach algorithm can give 50% less pessimistic results compared to Network Calculus algorithm, but the execution time using conventional computational methods can be prohibitive.